Transceivers used, for example, for asynchronous serial communication, include circuitry for generating trapezoidal wave signals and for filtering noise in an output signal.
JP-A-2002-152015 discloses a charge-and-discharge circuit which includes two constant current circuits and a capacitor, with one constant current circuit connected in series to the capacitor being adapted to charge the capacitor and another constant current circuit connected in parallel to the capacitor being adapted to discharge the capacitor (Shown in FIG. 1 of this publication). This charge-and-discharge circuit is intended to produce a trapezoidal wave voltage, while by connecting a switch circuit between the capacitor and the discharging constant current circuit and turning on and off the switch circuit in response to an input signal having two logical levels, the circuit can be used as a noise filtering circuit for the input signal.
JP-A-9-261016 discloses a trapezoidal wave signal generator for producing a trapezoidal wave signal with suppressed harmonic components by utilization of the characteristics of MOS transistors.
FIG. 13 illustrates an exemplary circuit arrangement 1 for producing a trapezoidal wave voltage and for eliminating the noise included in the reception signal received during, for example, asynchronous serial communication. This circuit is configured by use of the charge/discharge circuit disclosed in JP-A-2002-152015. The circuit 1 may be used as a preceding stage of a driver circuit of asynchronous serial communication to suppress the noise generation attributable to sharp signal variations on the communication line.
The circuit 1 includes transistors T1 and T2 respectively connected to constant current circuits 3 and 4. Together, transistors T1 and T2 constitute a current mirror circuit 2. A transistor T3, which operates as the above-mentioned switch circuit, is connected in parallel to the transistor T1. The transistor T3 is turned on and off by an input voltage signal Vin, which is derived in level from the reception signal. A capacitor C1 is connected in parallel to the transistor T2. A logical bi-leveling circuit 5, which causes a signal to have two logical levels, receives a voltage Vc across the capacitor C1 and generates a 2-level output voltage signal Vo. The constant current circuits 3 and 4 are designed such that the output current I1 of circuit 3 is twice the output current I2 of circuit 4.
In operation, when the input voltage Vin turns from a low to a high level, the transistor T3 turns on and transistors T1 and T2 turn off, which causes the capacitor C1 to be charged by the output current I2 of the constant current circuit 4. Consequently, the output voltage Vo rises at a constant rate. When the input voltage Vin turns from a high to a low level, the transistor T3 turns off and transistors T1 and T2 turn on, causing the capacitor C1 to be discharged by a differential current (I1-I2) between the current I1 flowing through the transistor T2 and the output current I2 of the constant current circuit 4. Consequently, the output voltage Vo falls at a constant rate.
However, the resulting output voltage Vo having a trapezoidal waveform will include many harmonic components created at level transitions of the input voltage Vin. Therefore, when this circuit is used for a vehicle on-board network it may not be able to suppress noise generation interfering with the on-board radio.
FIG. 14 shows the signal waveforms of the circuit 1. More particularly, FIG. 14 shows: (a) input voltage Vin, (b) capacitor C1 voltage Vc, and (c) output voltage Vo of the bi-leveling circuit 5. The capacitor voltage Vc immediately falls to a negative voltage −VF (VF: base-emitter voltage) when the input voltage Vin rises from the low level to the high level and thereafter Vc progressively rises. This voltage fall is caused by base-to-collector coupling attributed to the base-collector capacitance Cbc (shown by the dotted line in FIG. 13) of transistor T2. A variation of base voltage results directly in a variation of collector voltage.
Accordingly, a time difference ta emerges from the initial time at which the input voltage Vin makes a low-to-high transition and the time at which the capacitor voltage Vc rises to the rising threshold voltage V TH (3 V) of the bi-leveling circuit 5. A time difference tb also emerges from the time at which the input voltage Vin makes a high-to-low transition and the time at which the capacitor voltage Vc falls from 5 V to the falling threshold voltage VTL (2 V) of the circuit 5. Consequently, not only is there a delay between the output voltage Vo and the input voltage Vin, but the waveform also differs from Vin. This delay and waveform difference may cause a data reception error at the reception register, which is the next stage of the bi-leveling circuit 5.
The above-mentioned case demonstrates the need of control for equalizing the rise time and fall time of a signal, More generally, a filter circuit is needed for accurately settling the time discordant characteristics in terms of signal rising/falling time span between the input and output signals.